1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device and method of arranging a pad thereof that increases heat emission efficiency.
2. Description of Related Art
In a conventional semiconductor memory device, a pad includes an upper pad and a lower pad, and dummy layers are disposed under the pad in order to adjust the step height relative to adjacent portions and alleviate stress applied during a wire bonding process for connecting the pad to pins. However, in the conventional semiconductor memory device, insulating layers are interposed between the dummy layers. Thus, heat is not properly dissipated from the semiconductor memory device because the insulating layers have low thermal conductivity. As a result, the semiconductor memory device becomes less efficient in dissipating heat, and its operating performance becomes poorer.
For this reason, many attempts are being made to improve the heat-dissipation efficiency of the semiconductor memory device. Furthermore, high-speed semiconductor memory devices need to improve the heat-dissipation efficiency all the more because as the semiconductor memory devices operate faster, more heat is generated.
FIG. 1A is a plan view of a pad of a conventional semiconductor memory device, and FIG. 1B is a cross-sectional view taken along line X-X′ of FIG. 1A. Referring to FIGS. 1A and 1B, an active region 12 is disposed in a substrate 10, a first insulating layer 14 is disposed on the active region 12, and a gate poly layer 16 is disposed on the first insulating layer 14. A second insulating layer 18 is disposed on the gate poly layer 16, a plate poly layer 20 is disposed on the second insulating layer 18, and a third insulating layer 22 is disposed on the plate poly layer 20. A first metal layer 24 is disposed on the third insulating layer 22, a via contact 26 is disposed on the first metal layer 24, and a second metal layer 28 is disposed on the via contact 26.
In FIGS. 1A and 1B, the first metal layer 24 forms a lower pad, and the second metal layer 28 forms an upper pad, and the lower and upper pads are connected by the via contact 26 interposed between the first and second metal layers 24 and 28. Also, the third insulating layer 22, the plate poly layer 20, the second insulating layer 18, the gate poly layer 16, and the first insulating layer 14, which are formed under the first metal layer 24, are dummy layers that serve to adjust the step height with adjacent regions in the semiconductor device and alleviate stress applied during a wire bonding process for connecting the upper pad to pins (not shown).
In the pad of the conventional semiconductor device, when heat is generated in the substrate 10, it propagates through the active region 12 to the first insulating layer 14, the gate poly layer 16, the second insulating layer 18, the plate poly layer 20, and the third insulating layer 22, and the heat propagated to the third insulating layer 22 is transmitted through the first metal layer 24, the via contact 26, and the second metal layer 28 and dissipated from the semiconductor device.
However, the conventional semiconductor memory device cannot effectively dissipate the heat generated therein because the first, second, and third insulating layers used as dummy layers have low thermal conductivity.